STM32C532FB

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产品概述

描述

The STM32C53xxx devices are general purpose microcontrollers family (STM32C5 series) based on the high‑performance Arm^® Cortex^®-M33 32-bit RISC core. They operate at a frequency of up to 144 MHz.

The Cortex^®-M33 core features a single‑precision floating‑point unit (FPU) that supports all the Arm^® single‑precision data‑processing instructions and all the data types.

The Cortex^®-M33 core also implements a full set of digital signal processing (DSP) instructions and a memory protection unit (MPU) that enhances the application security.

The devices embed high‑speed memories (up to 256‑Kbyte flash memory and 64‑Kbyte SRAM), and an extensive range of enhanced I/Os, peripherals connected to three APB buses, three AHB buses, and a 32‑bit multi‑AHB bus matrix.

The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, and hide protection areas.

The devices embed several peripherals reinforcing security:

HASH hardware accelerator
True random number generator

The devices offer one 12‑bit ADC, two DAC channels, two comparators, one operational amplifier, a low‑power RTC, one 32‑bit general‑purpose timer, two 16‑bit PWM timers dedicated to motor control, two 16‑bit general‑purpose timers, two 16‑bit basic timers, and one 16‑bit low‑power timer.

The devices also feature standard and advanced communication interfaces such as:

One I2C
One I3C
Two SPIs with muxed full-duplex I2S
Two USARTs, two UARTs, and one low‑power UART
Two FDCANs
One USB full‑speed

The devices operate in the -40 to +105 °C (+140 °C junction) temperature ranges from a 2.7 to 3.6 V power supply.

A comprehensive set of power‑saving modes allows the design of low‑power applications.

The devices offer multiple packages from 20 to 64 pins.

所有功能
Includes ST state-of-the-art patented technology.

内核

32-bit Arm^® Cortex^®-M33 CPU with FPU, frequency up to 144 MHz, MPU, and DSP instructions

Benchmarks

ART Accelerator

8-Kbyte instruction cache allowing 0-wait-state execution from flash and up to CPU maximum speed

存储器

Up to 256‑Kbyte flash memory with ECC, 2 banks read-while-write

64-Kbyte SRAM including 32 Kbytes with ECC

64-Kbyte user data flash memory, 2 banks

4.5-Kbyte OTP (one-time programmable)

Clock, reset, and supply management

2.7 V to 3.6 V application supply and I/O

POR, PDR, and PVD

Embedded regulator (LDO)

Internal oscillators: 144 MHz HSI (with ± 1% accuracy over temperature range [-20°C : 130°C])160/144/100 MHz PSI32 kHz LSI

External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE

Low-power modes: Sleep, Stop, and Standby

DMA controller to offload the CPU

2 x LPDMA with 8 channels (4 + 4)

Analog

1 × 12-bit ADC (12 external channels and 2 internal), up to 2.25 MSPS

2 × 12-bit DACs

2 × comparators

1 × Operational amplifier
Up to 10 timers

6 × 16-bit (including 2 × 16-bit advanced motor controls, 1 × low-power 16-bit timer available in Stop mode) and 1 × 32-bit timers

2 × watchdogs

1 × SysTick timer

RTC with hardware calendar, alarms, and calibration

Communication interfaces

Up to 1 × I2C FM+ interface (SMBus/PMBus)

Up to 1 × I3C

Up to 2 × USARTs (ISO7816 interface, LIN, IrDA, modem control), 2 × UARTs, and 1 × LPUART

Up to 2 × SPIs with muxed with full‑duplex I2S for audio class accuracy via external clock and up to 2 × additional SPIs from 2 × USARTs when configured in synchronous mode

2 × FDCANs

1 × USB 2.0 full-speed host and device

Low-power modes

Sleep, Stop, and Standby modes

Up to 52 I/O ports with interrupt capability

安保

HASH hardware accelerator (SHA-1, SHA-224, SHA-256, HMAC)

True random number generator, NIST SP800-90B compliant

96-bit unique ID

Flexible life-cycle scheme with RDP and password-protected regression

Mathematical coprocessor

CORDIC for trigonometric functions acceleration

Bootloader support on USART, FDCAN, USB, and SPI interfaces

All packages are ECOPACK2 compliant.
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