产品概要
描述
Stellar integration MCUs are designed to meet the requirements of domain controllers and ECUs with high integration, as required in the architectures of connected, updatable, automated, and electrified cars. They have superior real-time and safe performance (with the highest ASIL-D capability). Bringing hardware-based virtualization technology to MCUs, they ease the development and integration of multiple-source software on the same hardware while maximizing the resulting software performance. They offer high-efficiency OTA reprogramming capability with fast new image download and activation. They also provide high-speed security cryptographic services, for instance for network authentication.
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性能一览
- Highlights
- AEC-Q100 qualified
- SR6 integration MCUs:
- Have superior real-time and safe performance (with highest ASIL-D capability)
- Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance
- Have built-in no downtime OTA reprogramming capability (with built-in dual-image mechanism)
- Offer high-speed security cryptographic services, for example for network authentication
- Cores and accelerators
- 6 × 32-bit Cortex®‑R52+ cores (4 of them with checker cores, and 2 in split-lock configuration):
- Configurable as either 6 cores (4 of them in lockstep configuration) or 5 cores (all of them in lockstep configuration)
- Arm® v8-R compliant
- Single precision floating-point unit (FPU)
- New privilege level for real-time virtualization
- Up to 500 MHz
- 2 cores with Neon™ extensions (for example SIMD, dual precision FPU)
- 2 Cortex®‑M4 multipurpose accelerators running at up to 200 MHz, both in lockstep configuration
- 4 eDMA engines in lockstep configuration
- 6 × 32-bit Cortex®‑R52+ cores (4 of them with checker cores, and 2 in split-lock configuration):
- Memories
- xMemory: up to 40 MB extensible on-chip nonvolatile memory (NVM) depending on ordered part number:
- PCM (phase-change memory) as nonvolatile memory
- Up to 39 MB code NVM, with A/B swap OTA mechanism (up to 2× 19.5 MB)
- 1024 KB HSM-dedicated code NVM
- 640 KB data NVM (512 KB + 128 KB dedicated to HSM)
- Up to 9536 KB on-chip general-purpose SRAM
- xMemory: up to 40 MB extensible on-chip nonvolatile memory (NVM) depending on ordered part number:
- Security: 2nd generation hardware security module
- Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details)
- On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA)
- Symmetric and asymmetric cryptography processor
- High-performance lock-stepped AES-Light security subsystem for fast ASIL-D cryptographic services
- Safety: comprehensive new-generation ASIL-D safety concept
- New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities
- Complete hardware virtualization architecture built on Cortex®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications)
- Device standby/low-power modes
- Versatile low-power modes
- Ultra-low power: standby mode for lowest quiescent current with optimized active subsystem (for example standby RAM) and wake-up capability
- Smart low-power: smart power mode with Cortex®‑M4 subsystem, extended communications interfaces, and ADC peripheral
- Peripheral, I/O, and communication interfaces
- 28 LINFlexD modules
- 2 dual-channel FlexRay controllers
- 10 queued serial peripheral interface (SPIQ) modules
- 2 DSPI with shifted PWM serialization support for lighting applications
- 2 I²C interfaces
- 2 SENT modules (15 channels each)
- 2 PSI5 modules (2 channels each)
- Enhanced analog-to-digital converter system with:
- 8 separate 12-bit SAR analog converters (including one supervisor/safety ADC).
- 1× 9-bit SAR analog converter for device standby/low-power mode
- Interconnection with GTM timer for autonomous ADC/GTM subsystem operation
- Advanced timed I/O capability:
- Generic timer module (GTM4154)
- Communication interfaces:
- Two 10/100/1000 Mbit/s Ethernet controllers compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and EMC optimized SGMII
- 19 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M_TTCAN), all supporting flexible data rate (ISO CAN FD®)
- 2 CAN XL®
- External memory interfaces
- 2 octo-SPI IPs to support HyperBus™ memory (flash/RAM) devices
- 1 SDMMC interface
- Highlights
EDA Symbols, Footprints and 3D Models
STMicroelectronics - SR6G7EC6
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Quality and Reliability
| Part Number | Marketing Status | Package | Grade | 符合RoHS级别 | Material Declaration** |
|---|---|---|---|---|---|
| SR6G7EC6XMC5FX0R | Proposal 市场提案，仅供征询客户意见。不作设计或生产承诺。 | FPBGA 476 21.3X21.3X1.8 | Industrial | - | |
SR6G7EC6XMC5FX0R
Package:
FPBGA 476 21.3X21.3X1.8Material Declaration**:
(**) st.com上提供的材料声明表单可能是基于包装系列中最常用的封装的通用文档。因此，它们可能不是100%适用于特定的设备。有关特定设备的信息，请联系 销售支持。
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Sample & Buy
| Part Number | 供货状态 | Budgetary Price (US$)*/Qty | 从ST订购 | Order from distributors | Package | Packing Type | RoHS | Country of Origin | ECCN (US) | ECCN (EU) | Operating temperature (°C) | Operating Temperature (°C) (max) | CPU Clock Frequency (MHz) (max) | Flash Size (kB) (Data) | ||
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| SR6G7EC6XMC5FX0R | | | distributors 无法联系到经销商，请联系我们的销售办事处 |
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SR6G7EC6XMC5FX0R Proposal