产品概述
描述
The STLVD111 is a low skew programmable 1 to 10 differential LVDS driver, designed for clock distribution. The select signal is fanned out to 10 identical differential outputs.
The STLVD111 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The STLVD111 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device.
The STLVD111 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can take advantage of the device’s performance to distribute low skew clocks across the backplane or the board.
-
所有功能
- High signalling rate capability (exceeds 622MHz)
- Low voltage VCC range of 2.375V to 2.625V
- Programmable drivers power off control
- 100ps part-to part skew
- Differential design
- 50ps bank skew
- Reference voltage available output VBB
- Support open, short and terminated input fail-safe (low output state)
- Meets LVDS spec. for driver outputs and receiver inputs
EDA符号、封装和3D模型
意法半导体 - STLVD111B
Speed up your design by downloading all the EDA symbols, footprints and 3D models for your application. You have access to a large number of CAD formats to fit with your design toolchain.
Please select one model supplier :
符号
封装
3D模型