产品概述
描述
Stellar integration MCUs are designed to meet the requirements of domain controllers and ECUs with high integration, as required in the architectures of connected, updatable, automated, and electrified cars. They have superior real-time and safe performance (with the highest ASIL-D capability). Bringing hardware-based virtualization technology to MCUs, they ease the development and integration of multiple-source software on the same hardware while maximizing the resulting software performance. They offer high-efficiency OTA reprogramming capability with fast new image download and activation. They also provide high-speed security cryptographic services, for instance for network authentication.
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所有功能
- Highlights
- AEC-Q100 qualified
- SR6 integration MCUs:
- Have superior real-time and safe performance (with highest ASIL-D capability)
- Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance
- Have built-in no downtime OTA reprogramming capability (with built-in dual-image mechanism)
- Offer high-speed security cryptographic services, for example for network authentication
- Cores and accelerators
- 4 × 32-bit Cortex®‑R52+ cores (2 in split-lock configuration):
- Configurable as either 4 cores (2 of them in lockstep configuration) or 3 cores (all of them in lockstep configuration)
- Arm® v8-R compliant
- Single precision floating-point unit (FPU)
- New privilege level for real-time virtualization
- Up to 500 MHz
- 1 Cortex®‑M4 multipurpose accelerator running at up to 200 MHz, in lockstep configuration
- 4 eDMA engines
- 4 × 32-bit Cortex®‑R52+ cores (2 in split-lock configuration):
- Neural processing unit
- Neural ART Accelerator™ 11
- Energy efficient NPU capable of accelerating a wide range of neural network models
- 存储器
- xMemory: up to 19.5 MB extensible on-chip nonvolatile memory (NVM) depending on ordered part number:
- PCM (phase-change memory) as nonvolatile memory
- Up to 19 MB code NVM, with A/B swap OTA mechanism (up to 2× 9.5 MB)
- 512 KB HSM-dedicated code NVM
- 384 KB data NVM (256 KB + 128 KB dedicated to HSM)
- Up to 1792 KB on-chip general-purpose SRAM
- xMemory: up to 19.5 MB extensible on-chip nonvolatile memory (NVM) depending on ordered part number:
- Security: 2nd generation hardware security module
- Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details)
- On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA)
- Symmetric and asymmetric cryptography processor
- High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services
- Safety: comprehensive new-generation ASIL-D safety concept
- New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities
- Complete hardware virtualization architecture built on Cortex®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications)
- Device standby/low-power modes
- Versatile low-power modes
- Ultra-low power: standby mode for lowest quiescent current with optimized active subsystem (for example standby RAM) and wake-up capability
- Smart low-power: smart power mode with Cortex®‑M4 subsystem, extended communications interfaces, and ADC peripheral
- Peripheral, I/O, and communication interfaces
- 8 LINFlexD modules
- 1 dual-channel FlexRay controller
- 10 queued serial peripheral interface (SPIQ) modules
- 2 microsecond channels (MSC)
- 2 I²C interfaces
- 2 SENT modules (10 channels each)
- 2 PSI5 modules (1 channel each)
- Enhanced analog-to-digital converter system with:
- 12 separate 12-bit SAR analog converters (including one supervisor/safety ADC).
- 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode
- 1× 9-bit SAR analog converter for device standby/low-power mode
- 10 separate 16-bit sigma-delta analog converters with embedded DSP processor on each SDADC
- Enhanced interconnection with GTM timer for autonomous ADC/GTM subsystem operation
- Advanced timed I/O capability:
- Generic timer module (GTM4134)
- High-resolution timer
- Communication interfaces:
- One 10/100/1000 Mbit/s Ethernet controller compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and supporting 10BASE-T1S with OPEN Alliance 3-pin (OA3p) interface
- 8 modular controller area network (MCAN) modules, supporting CAN classic and CAN FD®
- 2 XS_CAN modules supporting CAN classic, CAN FD® and CAN XL®
- Highlights
EDA符号、封装和3D模型
意法半导体 - SR6P3EC4
Speed up your design by downloading all the EDA symbols, footprints and 3D models for your application. You have access to a large number of CAD formats to fit with your design toolchain.
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符号
封装
3D模型
质量与可靠性
| 料号 | Marketing Status | 包 | 等级规格 | 符合RoHS级别 | 材料声明** |
|---|---|---|---|---|---|
| SR6P3EC4XMC5FX0R | 目标 | FPBGA 17X17X1.8 292 B0.55 P0.8 | Automotive Safety Cybersecurity | Ecopack2 | |
SR6P3EC4XMC5FX0R
Package:
FPBGA 17X17X1.8 292 B0.55 P0.8Material Declaration**:
(**) st.com上提供的材料声明表单可能是基于包装系列中最常用的封装的通用文档。因此，它们可能不是100%适用于特定的设备。有关特定设备的信息，请联系 销售支持。
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样片和购买
| 料号 | 供货状态 | Budgetary Price (US$)*/Qty | 从ST订购 | Order from distributors | 包 | 包装类型 | RoHS | Country of Origin | ECCN (US) | ECCN (EU) | Operating temperature (°C) | Operating Temperature (°C) (max) | CPU Clock Frequency (MHz) (max) | Flash Size (kB) (Data) | ||
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| SR6P3EC4XMC5FX0R | | | distributors 无法联系到经销商，请联系我们的销售办事处 |
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