产品概述
描述
The chip is a fully integrated RF front-end able to down-convert the GPS L1 signal from 1575.42 MHz to 4.092 MHz.
The IF signal is converted by a two bit ADC. Sign (SIGN), Magnitude (MAG) and the 16.368 MHz sampling clock (GPS_CLK) are provided to the baseband.
The magnitude data is internally integrated in order to control the variable gain amplifiers in accordance to the RF input signal strength.
An excellent quality of reception in critical environments is ensured by the good noise figure and linearity of the receiver.
The on-chip oscillator supports crystal frequencies in the range of 10 MHz to 40 MHz. It is able to support TCXO providing also a buffered copy of the oscillator frequency.
The chip, using STMicroelectronics BiCMOS SiGe technology, is housed in a QFN-32 package.
-
所有功能
- Low IF architecture (fIF= 4fO)
- Minimum external components
- VGA gain internally regulated
- On chip programmable PLL
- Typ. 2.7 V supply voltage
- SPI interface
- 2 kV HBM ESD protected
- Compatible with GPS L1
- Standard QFN-32 package
- Low power for portable designs
EDA符号、封装和3D模型
意法半导体 - STA5620A
Speed up your design by downloading all the EDA symbols, footprints and 3D models for your application. You have access to a large number of CAD formats to fit with your design toolchain.
Please select one model supplier :
符号
封装
3D模型