STM32MP211C

描述

STM32MP21xC/F devices are based on the high-performance core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache, and a 128-Kbyte L2 cache. The Cortex®‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.

STM32MP21xC/F devices also embed a Cortex®-M33 32-bit RISC core operating at up to 300 MHz frequency. The Cortex®-M33 core features a floating-point unit (FPU) single precision which supports Arm® single-precision data-processing instructions, and data types. The Cortex®-M33 supports a full set of DSP instructions, TrustZone®, and a memory protection unit (MPU) which enhances application security.

STM32MP21xC/F devices provide an external SDRAM interface supporting external memories up to 4 Gbytes, 16‑bit DDR3L up to 800 MHz, 16‑bit LPDDR4, or DDR4 up to 800 MHz. The SDRAM content can be encrypted with AES-128 or AES-256 with SCA protection.

The devices incorporate high-speed embedded memories: 456 Kbytes of internal SRAM (including 256-Kbyte AXI SYSRAM), one bank of 64 Kbytes of AHB SRAM, 128 Kbytes of AHB SRAM in backup domain, and 8 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix, and a 128/64-bit multilayer AXI interconnect supporting access to internal and external memories.

Each device offers two ADCs, a low-power secure RTC, 12 general-purpose 16-bit timers, four general-purpose 32‑bit timers, two PWM timers for motor control, five low-power timers, two true random number generator (RNG), two cryptographic acceleration cells and secure AES coprocessor with side channel attack (SCA) protection.

The devices support four multifunction digital filters (MDF)