              STM32P496 L4-1M MICROCONTROLLER PROGRAMMING SERVICE OPTION LIST
                     		(Last update: January 2017, rel. 0.1)

Customer: xxxxxxxxxx
Address:  xxxxxxxxxx
          xxxxxxxxxx
Contact:  xxxxxxxxxx
Phone No: xxxxxxxxxx
Reference:xxxxxxxxxx
  
(N.B. The FASTROM code name is assigned by STMicroelectronics)
FASTROM code must be sent Intel extended format.

Device Type/Package (check only one option):
-------------|----------------|
FASTROM      |     Package    |
DEVICE       |                |
-------------|----------------|
STM32P4A6ZxT |[ ]LQFP144 20x20|
STM32P4A6VxT |[ ]LQFP100 14x14|
STM32P4A6RxT |[ ]LQFP64  10x10|
STM32P4A6VxY |[ ]WLCSP100     |
STM32P4A6AxI |[ ]UFBGA169 7x7 |
STM32P4A6QxI |[ ]UFBGA132 7x7 |
-------------|----------------|

Conditioning :	[ ] Tray	[ ] Tape & Reel.

Standard Temp. Range (Please refer to datasheet for specific sales conditions): 
[  ] -40C to +85C  (suffix 6)
[  ] -40-C to +105-C (suffix 7)
[  ] -40-C to +125-C (suffix 3)

Special Marking:        [ ] No  [ ] Yes : "xxxxxxxx" 
(special charge apply)

LQFP144 20x20 :  14 characters maximum
LQFP100 14x14 :  12 characters maximum
LQFP64  10x10 :  10 characters maximum
WLCSP100      :  8 characters maximum
UFBGA169      :  8 characters maximum
UFBGA100      :  10 characters maximum


Authorized characters are letters, digits, '.', '-', '/' and spaces only. 

Device Memory Size (check only one option):
		[ ]1MB - STM32P4A6xGx
		[ ]512KB - STM32P4A6xEx

The memory size to program can be less or equal to the device memory size.

Select padding value for unused program memory :
[X]0xFFFF Fixed value
[ ]0x0F0F SVC instruction  opcode (Supervisor Call) (not available now)

Start address: 0x0800 0000   (default is flash base address 0x0800 0000)

USER option byte  
[selection] 'value' "meaning"

nBOOT0 - Boot selection configuration
  [ ] '0' "nBOOT0 = 0"               [ ] '1' "nBOOT0 = 1"
nSWBOOT0 - Boot selection configuration
  [ ] '0' "BOOT0 = nBOOT0"           [ ] '1' "BOOT0 = PH3/BOOT0 pin"
SRAM2_RST - SRAM2 Erase when system reset 
  [ ] '0' "SRAM2 erased"             [ ] '1' "SRAM2 not erased"
SRAM2_PE - SRAM2 parity check configuration   
  [ ] '0' "Enabled"                  [ ] '1' "Disabled"
nBOOT1 - Boot selection configuration
  [ ] '0' "SRAM"                     [ ] '1' "Bootloader"
DUALBANK - Dual Bank on 1 MB Flash memory devices
  [ ] '0' "Single-bank"              [ ] '1' "Dual-bank"
BFB2 - Dual Bank boot
  [ ] '0' "Disabled"              [ ] '1' "Enabled"
WWDG_SW - Software / Hardware watchdog activation 
  [ ] '0' "Hardware"                 [ ] '1' "Software" 
IWDG_STDBY - Independent watchdog counter freeze in Standby mode 
  [ ] '0' "Frozen"                   [ ] '1' "Running" 
IWDG_STOP - Independent watchdog counter freeze in Stop mode 
  [ ] '0' "Frozen"                   [ ] '1' "Running" 
IWDG_SW - Software / Hardware watchdog activation 
  [ ] '0' "Hardware"                 [ ] '1' "Software" 
nRST_SHDW - Reset generated when entering Shutdown mode
  [ ] '0' "Reset"                    [ ] '1' "No Reset" 
nRST_STDBY - Reset generated when entering Standby mode
  [ ] '0' "Reset"                    [ ] '1' "No Reset" 
nRST_STOP - Reset generated when entering Stop mode         
  [ ] '0' "Reset"                    [ ] '1' "No Reset"
BOR_LEV - BOR reset level
  [ ] '000' BOR Level 0. Reset level threshold is around 1.7 V
  [ ] '001' BOR Level 1. Reset level threshold is around 2.0 V
  [ ] '010' BOR Level 2. Reset level threshold is around 2.2 V
  [ ] '011' BOR Level 3. Reset level threshold is around 2.5 V
  [ ] '100' BOR Level 4. Reset level threshold is around 2.8 V
RDP - Read Protection configuration   
[ ] '0xXX' Level1    [ ] '0xCC' "Level2"     [ ] '0xAA' "Disabled"

PCROP - Start address option byte Bank 1
PCROP1_STRT - bit 0 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 1 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 2 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 3 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 4 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 5 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 6 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 7 [ ] '0' [ ] '1' 

PCROP1_STRT - bit 8 [ ] '0' [ ] '1' 
PCROP1_STRT - bit 9 [ ] '0' [ ] '1' 
PCROP1_STRT - bit10 [ ] '0' [ ] '1' 
PCROP1_STRT - bit11 [ ] '0' [ ] '1' 
PCROP1_STRT - bit12 [ ] '0' [ ] '1' 
PCROP1_STRT - bit13 [ ] '0' [ ] '1' 
PCROP1_STRT - bit14 [ ] '0' [ ] '1' 
PCROP1_STRT - bit15 [ ] '0' [ ] '1' 

PCROP - End address option byte Bank 1
PCROP1_END - bit 0 [ ] '0' [ ] '1' 
PCROP1_END - bit 1 [ ] '0' [ ] '1' 
PCROP1_END - bit 2 [ ] '0' [ ] '1' 
PCROP1_END - bit 3 [ ] '0' [ ] '1' 
PCROP1_END - bit 4 [ ] '0' [ ] '1' 
PCROP1_END - bit 5 [ ] '0' [ ] '1' 
PCROP1_END - bit 6 [ ] '0' [ ] '1' 
PCROP1_END - bit 7 [ ] '0' [ ] '1' 

PCROP1_END - bit 8 [ ] '0' [ ] '1' 
PCROP1_END - bit 9 [ ] '0' [ ] '1' 
PCROP1_END - bit10 [ ] '0' [ ] '1' 
PCROP1_END - bit11 [ ] '0' [ ] '1' 
PCROP1_END - bit12 [ ] '0' [ ] '1' 
PCROP1_END - bit13 [ ] '0' [ ] '1' 
PCROP1_END - bit14 [ ] '0' [ ] '1' 
PCROP1_END - bit15 [ ] '0' [ ] '1' 

PCROP_RDP  - bit31 [ ] '0' [ ] '1' 

WRP1A - Area A write protection byte Bank 1
WRP1A_STRT - bit 0 [ ] '0' [ ] '1' 
WRP1A_STRT - bit 1 [ ] '0' [ ] '1' 
WRP1A_STRT - bit 2 [ ] '0' [ ] '1' 
WRP1A_STRT - bit 3 [ ] '0' [ ] '1' 
WRP1A_STRT - bit 4 [ ] '0' [ ] '1' 
WRP1A_STRT - bit 5 [ ] '0' [ ] '1' 
WRP1A_STRT - bit 6 [ ] '0' [ ] '1' 
WRP1A_STRT - bit 7 [ ] '0' [ ] '1' 

WRP1A_END - bit 16 [ ] '0' [ ] '1' 
WRP1A_END - bit 17 [ ] '0' [ ] '1' 
WRP1A_END - bit 18 [ ] '0' [ ] '1' 
WRP1A_END - bit 19 [ ] '0' [ ] '1' 
WRP1A_END - bit 20 [ ] '0' [ ] '1' 
WRP1A_END - bit 21 [ ] '0' [ ] '1' 
WRP1A_END - bit 22 [ ] '0' [ ] '1' 
WRP1A_END - bit 23 [ ] '0' [ ] '1' 

WRP1B - Area B write protection byte Bank 1
WRP1B_STRT - bit 0 [ ] '0' [ ] '1' 
WRP1B_STRT - bit 1 [ ] '0' [ ] '1' 
WRP1B_STRT - bit 2 [ ] '0' [ ] '1' 
WRP1B_STRT - bit 3 [ ] '0' [ ] '1' 
WRP1B_STRT - bit 4 [ ] '0' [ ] '1' 
WRP1B_STRT - bit 5 [ ] '0' [ ] '1' 
WRP1B_STRT - bit 6 [ ] '0' [ ] '1' 
WRP1B_STRT - bit 7 [ ] '0' [ ] '1' 

WRP1B_END - bit 16 [ ] '0' [ ] '1' 
WRP1B_END - bit 17 [ ] '0' [ ] '1' 
WRP1B_END - bit 18 [ ] '0' [ ] '1' 
WRP1B_END - bit 19 [ ] '0' [ ] '1' 
WRP1B_END - bit 20 [ ] '0' [ ] '1' 
WRP1B_END - bit 21 [ ] '0' [ ] '1' 
WRP1B_END - bit 22 [ ] '0' [ ] '1' 
WRP1B_END - bit 23 [ ] '0' [ ] '1' 


PCROP - Start address option byte Bank 2
PCROP2_STRT - bit 0 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 1 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 2 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 3 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 4 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 5 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 6 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 7 [ ] '0' [ ] '1' 

PCROP2_STRT - bit 8 [ ] '0' [ ] '1' 
PCROP2_STRT - bit 9 [ ] '0' [ ] '1' 
PCROP2_STRT - bit10 [ ] '0' [ ] '1' 
PCROP2_STRT - bit11 [ ] '0' [ ] '1' 
PCROP2_STRT - bit12 [ ] '0' [ ] '1' 
PCROP2_STRT - bit13 [ ] '0' [ ] '1' 
PCROP2_STRT - bit14 [ ] '0' [ ] '1' 
PCROP2_STRT - bit15 [ ] '0' [ ] '1' 

PCROP - End address option byte Bank 2
PCROP2_END - bit 0 [ ] '0' [ ] '1' 
PCROP2_END - bit 1 [ ] '0' [ ] '1' 
PCROP2_END - bit 2 [ ] '0' [ ] '1' 
PCROP2_END - bit 3 [ ] '0' [ ] '1' 
PCROP2_END - bit 4 [ ] '0' [ ] '1' 
PCROP2_END - bit 5 [ ] '0' [ ] '1' 
PCROP2_END - bit 6 [ ] '0' [ ] '1' 
PCROP2_END - bit 7 [ ] '0' [ ] '1' 

PCROP2_END - bit 8 [ ] '0' [ ] '1' 
PCROP2_END - bit 9 [ ] '0' [ ] '1' 
PCROP2_END - bit10 [ ] '0' [ ] '1' 
PCROP2_END - bit11 [ ] '0' [ ] '1' 
PCROP2_END - bit12 [ ] '0' [ ] '1' 
PCROP2_END - bit13 [ ] '0' [ ] '1' 
PCROP2_END - bit14 [ ] '0' [ ] '1' 
PCROP2_END - bit15 [ ] '0' [ ] '1' 

WRP2A - Area A write protection byte Bank 1
WRP2A_STRT - bit 0 [ ] '0' [ ] '1' 
WRP2A_STRT - bit 1 [ ] '0' [ ] '1' 
WRP2A_STRT - bit 2 [ ] '0' [ ] '1' 
WRP2A_STRT - bit 3 [ ] '0' [ ] '1' 
WRP2A_STRT - bit 4 [ ] '0' [ ] '1' 
WRP2A_STRT - bit 5 [ ] '0' [ ] '1' 
WRP2A_STRT - bit 6 [ ] '0' [ ] '1' 
WRP2A_STRT - bit 7 [ ] '0' [ ] '1' 

WRP2A_END - bit 16 [ ] '0' [ ] '1' 
WRP2A_END - bit 17 [ ] '0' [ ] '1' 
WRP2A_END - bit 18 [ ] '0' [ ] '1' 
WRP2A_END - bit 19 [ ] '0' [ ] '1' 
WRP2A_END - bit 20 [ ] '0' [ ] '1' 
WRP2A_END - bit 21 [ ] '0' [ ] '1' 
WRP2A_END - bit 22 [ ] '0' [ ] '1' 
WRP2A_END - bit 23 [ ] '0' [ ] '1' 

WRP2B - Area B write protection byte Bank 1
WRP2B_STRT - bit 0 [ ] '0' [ ] '1' 
WRP2B_STRT - bit 1 [ ] '0' [ ] '1' 
WRP2B_STRT - bit 2 [ ] '0' [ ] '1' 
WRP2B_STRT - bit 3 [ ] '0' [ ] '1' 
WRP2B_STRT - bit 4 [ ] '0' [ ] '1' 
WRP2B_STRT - bit 5 [ ] '0' [ ] '1' 
WRP2B_STRT - bit 6 [ ] '0' [ ] '1' 
WRP2B_STRT - bit 7 [ ] '0' [ ] '1' 

WRP2B_END - bit 16 [ ] '0' [ ] '1' 
WRP2B_END - bit 17 [ ] '0' [ ] '1' 
WRP2B_END - bit 18 [ ] '0' [ ] '1' 
WRP2B_END - bit 19 [ ] '0' [ ] '1' 
WRP2B_END - bit 20 [ ] '0' [ ] '1' 
WRP2B_END - bit 21 [ ] '0' [ ] '1' 
WRP2B_END - bit 22 [ ] '0' [ ] '1' 
WRP2B_END - bit 23 [ ] '0' [ ] '1'
Please refer to the device reference manual for more information.


Date 25-January-2017		Signature   . . . . . . . . . . . . . .

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