*SD4933_rev1_0
*March 10 ,2011
*STMicroelectronics 
*port 1 = GATE , 2 = Drain , 3 = Source
*
.SUBCKT  SD4933 9 20 30
Rseries 9 10     1.04
LGATE1 10  11     .3N
RGATE1 11  12     .3
CG1    10  30     .5P
CRSS1  12  17    8P
CISS1  12  14     570P
LS1    14  30     0.3N
CS1    14  30     .02P
R1     17  13     100K
LD1    17  20     .1N
CD1    20  30     .5P
MOS1   13  12  14  14     mos_4926  L=.2UM W= 925mM 
JFET1  17  14  13         jf_4926		  
DBODY1 14  17             d_4926
LGATE2 10  11     .3N
RGATE2 11  12     .3
CG2    10  30     .5P
CRSS2  12  17     8p
CISS2  12  14     570P
LS2    14  30     0.3N
CS2    14  30     .02P
R2     17  13     100K
LD2    17  20     .1N
CD2    20  30     .5P
MOS2   13  12  14  14     mos_4926  L=.2UM W= 925mM 
JFET2  17  14  13         jf_4926		  
DBODY2 14  17             d_4926		  		    

.MODEL mos_4926 nmos (vto=2.5 KP=.71E-6 LAMBDA=1 RD=0.1001 RS=0.1001)
.MODEL jf_4926  njf  (VTO=-6 BETA=3.26 LAMBDA=3 Rd=.09 Rs=.09)
.MODEL d_4926  d    (CJO=1050p RS=0.25 VJ=.6 M=0.416 BV=255)

.ENDS

