* Vertical DMOS , Low Rds(on) process patent numbers US6750512,EP1296378 
*Large Signal Model REVISION 0 jprit  May 29 2008 
*STMicroelectronics
*RF Product Development and Characterization
*Quakertown,PA,USA
*node 10 = Gate
*node 20 = Drain
.SUBCKT sd3931/10  20  10  30
lg     10  11  0.3N
rg     11  12  0.2
cg     10  30  0.01P
crss   12  17  6P
ciss   12  14  480P
Ls     14  30  0.3N 
cs     14  30  0.02P
R      17  13  100K
ld     17  20  .1N
cd     20  30  0.02P
MOS    13  12  14  14 pps4925 L=.2u w=0.925       
JFET   17  14  13     pps4925j                     
DBODY  14  17         pps4925d                    
 
.MODEL pps4925 nmos (vto=2.5 KP=0.71E-6 LAMBDA=1.0 RD=0.12 RS=0.12)
.MODEL pps4925j  njf  (VTO=-5 BETA=3.26 LAMBDA=3)
.MODEL pps4925d  d    (CJO=1050p RS=0.25 VJ=0.6 M=0.4 BV=260)
.ENDS