The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology.

The clamping voltage V_CL can be calculated as follow:

V_CL+ = V_TRANSIL + V_F for positive surges

V_CL- = - V_F for negative surges

with: V_F = V_T + R_d.Ip

(V_F forward drop voltage) / (V_T forward drop threshold voltage)

and V_TRANSIL = V_BR + R_{d_TRANSIL}.I_P

Calculation example

We assume that the value of the dynamic resistance of the clamping diode is typically:

R_d = 0.5 Ω and V_T = 1.1 V

We assume that the value of the dynamic resistance of the transil diode is typically:

R_{d_TRANSIL} = 0.5 Ω and V_BR = 6.1 V For an IEC 61000-4-2 surge level 4 (Contact Discharge: V_g = 8 kV, R_g = 330 Ω), V_BUS = +5 V, and if in first approximation, we assume that:

I_p = V_g / R_g = 24 A.

So, we find:

V_CL+ = +31.2 V

V_CL- = -13 V

If we consider that the connections from the pin V_BUS to V_CC, from I/O to data line and from GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances L_VBUS, L_I/O and L_GND of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (t_r = 1 ns), the voltage V_CL has an extra value equal to L_I/O.dl/dt + L_GND.dI/dt.

The dI/dt is calculated as:

dI/dt = I_p/t_r = 24 A/ns

The overvoltage due to the parasitic inductances is:

L_I/O.dl/dt = L_GND.dI/dt = 6 nH x 24 A/ns = 144 V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be:

V_CL+ = +31.2 + 144 + 144 = 319.2 V

V_CL- = -13.1 - 144 - 144 = -301.1 V

We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some recommendations have to be followed (see ).

While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 6 ESD behavior: layout optimization and Figure 5 ESD behavior: parasitic phenomena due to unsuitable layout for layout consideration).

The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on load R_L2 is α₂V_G2, in fact the real voltage at this point has got an extra value β₂₁V_G1. This part of the V_G1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ).

Figure 11 Analog crosstalk measurements shows the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see Figure 12 Analog crosstalk results).

As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (Figure 4 Frequency response) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies, for instance.

Figure 15 PSpice model shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined by the PSpice parameters given in Figure 16 PSpice parameters.