Tiny, clever, low power, 0.56-megapixel, monochrome  global shutter image sensor

The VD55G1 is a compact global shutter image sensor featuring a matrix of 804 x 704 pixels. With its global shutter operation, all pixels are synchronized to capture light at the same time. This feature gets rid of the motion blur that can affect rolling shutter image sensors when capturing changing or moving scenes.

Once the exposure is finished, each pixel information is transferred in a storage node, before being read and digitized one pixel row after the other. The image data are digitized using internal 10-bit ADCs. Additional gains can be applied before ADC stage (for example, analog gain) or after ADC stage (for example, digital gain). Following the digital conversion, various image preprocessing and correction algorithms can be applied into the sensor before data output, such as autoexposure or binning.

The image data are output as frames of RAW8 or RAW10 data through a MIPI CSI-2 interface. The sensor operates on the single MIPI CSI-2 lane.

The VD55G1 is synchronized to the rest of the system by means of an external clock, triggers, and general-purpose input/output (GPIO) signals, which enable synchronization of several sensor exposure starts or to control strobe light sources during exposure time.

The device is fully configurable through the I²C or I3C serial interfaces and provides flexible frame-to-frame parameter configuration changes via the use of programmable contexts. It also embeds a one-time programmable (OTP) nonvolatile memory. It should be written with 32-bit words for traceability and customer data. The dedicated space reserved for the user is at least 1 Kbit.

The VD55G1 is configured and controlled via an I²C interface. It operates in either fast mode (up to 400 kHz) or fast+ mode (up to 1 MHz) at 1.8 V or 1.2 V. After the CPU boot sequence, the default I²C configuration is fast mode plus with a sink capability set to 20 mA. Drive capability can be decreased to 4 mA (fast mode) by writing a dedicated register once the system has booted.

Device addressing uses a CCI protocol as per the I²C-bus specification and user manual (UM3224).

In addition to the CSI interface, the VD55G1 I3C can be used to output the image. The I3C allows the use of a host in cases where CSI is not supported, or when the CSI interface is already used by another device.

Depending on the I3C host, the theoretical maximum frame rates are the following:

In the case of the I3C image output, the host must be in real time to ensure that the data are read at a consistent data rate.

The device interface includes a MIPI I3C^SM SDR. Refer to the MIPI - I3C specification v1.0.

Refer to:

• MIPI CSI-2 version 1.3 with I3C CCI (as defined in CSI-2 v4.0.1).
• MIPI D-PHY specification v 1.1.

The power supplies required by the sensor are:

• 2.8 V for the analog blocks
• 1.8 V or 1.2 V for the digital I/Os
• 1.10 V for the core digital logic and MIPI CSI-2 output drivers

The pixel array requires different positive and negative voltages, all internally generated by charge pumps and regulators. Two voltage references, internally generated, need external decoupling capacitors.

The internal MCU handles the entire power management of the sensor to guarantee the lowest power consumption at any given time.

An input clock is required from an external digital clock source in the range of 6 MHz to 27 MHz.

The video pipe performs several features designed to ensure an image of high quality. These features include:

• Analog subsampling
• Pattern generation
• Dynamic defective pixel correction
• Dark calibration
• Autoexposure
• Digital binning
• Embedded status lines
• Output interface
• Context management
• Cropping
• Flexible PWL gamma

The device supports x2, x4, and x8 subsampling, which reduces overall image size and keeps the same FoV. Subsampling is applied vertically and horizontally during the ADC readout. Every two, every four, or every eight pixels are read. When subsampling is used, the frame rate can be increased by decreasing the frame length.

Binning and subsampling are mutually exclusive.

The pattern generation allows the insertion of digital patterns in the output frame for test and debug. Either:

• Whole or part of the active data is replaced with a pattern
• Dark lines are kept untouched

The available patterns are:

• Diagonal gray scale
• Pseudorandom data

Active pixels are corrected automatically by a dynamic algorithm embedded in the sensor ISP. This enables defect-free images straight out of the sensor without further algorithm development or processing resources. The advanced correction algorithm can correct singlet and couplet of defects and take into account local spatial gradients.

The correction strength evolves automatically with exposure time.

The pixel matrix has dedicated lines with shielded pixels that dynamically retrieve the dark level and subtract it from the active image. Temperature, exposure time, or gain changes are compensated. Temporal smoothing and fractional bit dithering are applied to avoid a sudden one-code step. This block also embeds a programmable digital gain control feature with a granularity of 1/256 followed by a configurable pedestal to offset the dark level along the ISP pipe.

The sensor integrates an autoexposure module to compute statistics on a given part of the active image. This module allows the exposure parameter to be changed accordingly.

The sensor can enable two concurrent autoexposure processing algorithms. They can be split over the four contexts. It continues computing statistics over frames whether the autoexposure feature is enabled or not.

Stable behavior of the autoexposure module requires that AE ROI, exposure conditions, and active scene illumination in contexts are homogeneous.

The digital binning process reduces the image resolution by a factor of 2 or 4 in each direction. Central and neighboring pixels are weighted to produce the digital binned image, avoiding special phase shifts and artifacts that may occur on the output image. Digital binning and subsampling are mutually exclusive.

The MCU has access to a bank of status registers. They are refreshed at each frame. They provide detailed information on the current state of the sensor. For example:

• Clock settings
• Cropping and orientation parameters
• Analog and digital gains
• Integration time
• Frame counter index
• Thermal sensor value

The embedded status lines content is a copy of this information. The OIF generates an embedded status line, which allows metadata to be sent through the MIPI image data interface. There are 512 bytes transmitted at the beginning of each frame. The length of the embedded status line can be stretched to equal the active line packet size. Transmission of the embedded data lines can be disabled by configuring a static register during SW_STANDBY state before streaming. The embeded data lines have their own programmable "data types" and "virtual channels".

The OIF embeds a single data lane MIPI D-PHY interface. It supports up to 1.2 Gb/s of data. RAW10 and RAW8 data formats are supported over the CSI2-OIF.

The OIF can output a combination of the following:

• Intelligent status lines
• Frame data

The sensor allows the configuration of up to four different rolling contexts (or frame setups). Parameters that can be specifically defined in a context are listed in the figure below.

Contexts can be chained one to another in an ending or non-ending sequence.

The host can accurately choose which area of the whole pixel array it receives. This reduces traffic on the CSI interface and saves processing time.

The sensor has multiple synchronization modes:

1. Leader mode
   • Image streaming starts right after the execution of a streaming initialization command sent over the I²C bus.
2. Follower mode
   • Using GPIO pulses
   • Using I²C and I3C triggering commands

The sensor provides four GPIOs:

• GPIO0 is used as a frame start synchronization signal or as a generic GPIO if not used for this function
• GPIO[1-3] are used as strobe output, PWM output, VSYNC or as a generic GPIO as per the configuration

All GPIO settings are fully configurable for the four context setups. Each output signal can be mapped to one or several of the GPIOs. All GPIOs have configurable polarity.

Data of Table 4 Example of functional use cases are provided for an integration time of 1 ms.

The figure below describes the variation of the power consumption as a function of the frame rate, at full resolution, and at different integration times.

The VD55G1 includes the ability for in-sensor background removal. Using the pixel combined with the read-out ensures there is no delay between the two exposures.

The VD55G1 embeds a disruptive streaming mode, where each pixel value is the difference between two times.

It can be used to measure motion, with a single frame, so with ultra-low latency (single frame) and no impact on power consumption.

This mode is done directly at pixel level with ultrashort timings so cannot be emulated by the host.

There is no host processing needed as the image is natively differential.

Output can be considered as event-like but still compatible with standard processing.

Differential value is signed, where the zero can be positioned anywhere in the range [0:1023], which is useful for motion estimation.

These differential frames can be interlaced with standard images. It is typically useful to combine both object detection (hands, eyes...) and motion estimation.

The VD55G1 includes an autonomous mode, which ensures power saving. It allows sensing the scene in lower power mode, without image output. When there is a significant change in the image, the sensor triggers a GPIO. Then the host can enable normal streaming and analyze the scene.

The VD55G1 supports an HDR feature, requiring a single frame, so with no impact on power and latency.

There are three categories of pixels; each group has its own integration time.

The VD55G1 outputs the raw image without recombining the HDR.

There are two options for the host:

• Compute an HDR image by recombining the pixels with different exposure.s
• Directly apply computer vision on the raw image.

The VD55G1 embeds a flexible piece-wise linear (PWL) look-up-table (LUT).

The LUT is defined by four points. Each point is positioned by X and Y values, as well as the slope to the next point.

In the table below, the die dimensions are after sawing. The optical center is with the die center as reference.

Dedicated additional capacitors are required to complete the circuit. These are listed in Table 9 Capacitor needs. Capacitor needs below. The capacitors should be selected to maintain their capacitance value within the indicated tolerance over the full range of maximum voltages, operating temperatures, and aging.

Capacitor values are based on capacitor positions (embedded in the camera module or external to the camera module).

External capacitors are required to properly filter out supply noise. Optimal reference in terms of value and size is subject to application board architecture and topology. The external capacitor values provided in the table below may be increased to compensate real supply noise.

For good PCB design practice, observe the following image sensor layout:

• Use power and ground planes to supply power to the sensor.
• Join grounds i.e. join AGND and DGND into one single, solid GND plane underneath the sensor.
• Connect this GND plane to the sensor pads with one via per GND pad.
• To minimize risk of emissions, shield all vias and tracks attached to supplies by their respective GND nets.
• Maximize copper fill on the power planes near the sensor and use vias to improve heat transfer from the sensor. Consider including additional heatsinks close to the sensor if it is to be used at high temperatures.
• Route the high-speed signal pairs of the MIPI CSI-2 interface with balanced and controlled impedance differential traces (50 Ω single-ended impedance, 100 Ω differential impedance). This is a requirement for high-speed signaling. Route each pair together and match them in length to target a maximum 10 ps skew.

CPNEG_IN and CPNEG_OUT must be connected together with a short track. The required decoupling capacitor shall be placed on this path and not on an isolated track.

CPPOS_IN and CPPOS_OUT must be connected together with a short track. The required decoupling capacitor shall be placed on this path and not on an isolated track.

The power on sequence must be done as follows:

1. Provide all the external supplies (VDDIO, VCORE, VANA) according to the device characteristics described in Electrical characteristics. As long as XSHUTDOWN is low, the device is in HW_STANDBY state.
2. External supplies can be switched on in any order, as well as CLKIN.
3. Set XSHUTDOWN to high.

The device has power-on-reset (POR) detection cells with hysteresis on VCORE and VDDIO power supplies. POR is released after a typical delay of 20 μs on the rising edge.

Bursts with a duration of less than 2 μs (typical) are ignored.

The power down sequence must be done as follows:

1. If the sensor is in STREAMING state, then set it to SW_STANDBY state and wait for the command to complete.
2. Set XSHUTDOWN to low.
3. External supplies can be switched off in any order, as well as CLKIN.

Quantum efficiency (QE) is the percentage of incident photons converted into electrons, representing the sensitivity of the pixels.

QE graph is measured at Tj=60°C.

The modulation transfer function (or MTF) measures the ability of the device to differentiate spatial frequencies. The MTF value represents the contrast restitution for the corresponding spatial frequency, hence describes the contrast attenuation. It is a sharpness indicator that quantifies to what extent the image sensor can capture and discriminate tiny detailed contrast of an object in the field of view.

The figure below presents the on-axis MTF, measured in a 100x100 pixels ROI with the slanted-edge method. Note that the Ny is the spatial Nyquist frequency. This describes the MTF properties of the sensor itself (without a lens).

MTF is measured at ambient temperature.

Each pixel of the matrix has its own micro lens covering it.

The purpose of the microlens is to concentrate and optimize photon capture passing through the module lens down to the photodiode.

The light beam has an incidence angle change when passing through the module lens, increasing from center to periphery. This is the chief ray angle (CRA).

To compensate the change of CRA over the matrix, the microlens position over the pixels progressively shifts from matrix center to matrix borders.

The design of the sensor microlens shift is optimized for matching a lens with CRA of 30° at the corners, and follows a linear shift shape.

It is recommended to match the CRA of the lens with the CRA of the image sensor to maximize image quality. Featuring advanced BSI pixel technology, the VD55G1 provides high relative illumination (RI) uniformity up to the image corners, which enables users to select lenses with different CRA with limited impact.

The following figure presents the CRA tolerance range in lens selection for maintaining RI uniformity over 90% across the image.

The electrical characteristics have been measured under the following conditions:

• Full resolution (804x704 pixels)
• Nominal power supply levels and nominal voltage
• External clock at 12 MHz
• Full speed (168 fps)
• 1.2 Gbit/second on MIPI
• Junction temperature at 60°C
• Integration time = 376 µs

Values below are measured for the conditions listed in Electrical characteristics, but they also include process variability.

The values in Table 15 Maximum supply consumption are measured for the worst conditions of process, voltage, and junction temperature (85°C). They are evaluated on a limited number of devices.

It is evaluated on one device.

The curves on the graph below cover different devices tested over different voltage conditions (nominal or maximum).

It is evaluated on a limited number of devices.

Image sensors require stable power to ensure high-quality image capture, because fluctuations in power can lead to noise in the images. To ensure optimal performance of image sensors, it is important to provide a power supply that has a minimum spurious voltage.

The AC ripple parameter pertains to the sensor's external power sources. It applies to the voltage regulators powering the sensor. The table below defines the limits for permissible residual ripple.

These parameters are specified by design.

The CLKIN input is for all voltage and temperature conditions.

The digital inputs are over process variations at 60°C.

The digital outputs are over process variations at 60°C.

I²C timing and voltage conform with the norm: UM10204-I2C-bus specification and user manual, Rev. 6, 4 April 2014.

It is evaluated on a limited number of devices.

I3C timing and voltage conform with the norm :MIPI alliance Errata 02 for MIPI I3C Specification version 1.1.1, 10 March 2022.

It is evaluated on a limited number of devices.

The CSI-2 interface conforms with the MIPI DPHY specification v1.1.

It is evaluated on a limited number of devices.

Tested dice are delivered as sawn dice, which are reconstructed into a wafer format on UV-tape, and delivered on a metallic ring (see figure below). The frames are packed in plastic containers, each including a maximum of 13 double-spaced reconstructed wafer rings. A mapping information file is also provided for localizing dice that may have been damaged during wafer reconstruction on sticking foil.

Store all packing material in an appropriate indoor area. This is to prevent any dust and/or damage from the sun, external light, and physical shocks.

Keep the temperature between 15ºC and 35ºC.

Keep the relative humidity range between 10% and 70% maximum.

Store the reconstructed wafers under vacuum, in their original supplied sealed packing until they are used.

After the packing seal is broken, store the reconstructed wafers under nitrogen (N2) within dedicated closed shelves until they are processed.

Use the trace code to count the storage time. It is written on the package label.

The maximum storage time of the reconstructed wafer is:

• Six months from the trace code date. This is when the wafer is kept in the original sealed packing.
• One week from the trace code date. This is when the original packing seal is open.

The maximum storage time defines the maximum time that can be waited for reconstructed wafer processing. Processing may be for picking and placing, and module integration. If the maximum storage time is not respected, safe processing is not guaranteed.