This document applies to the Arm_®-based devices. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Electromagnetic compatibility (EMC) is the capability of a system to work properly, undisturbed by the electromagnetic phenomena present in its normal environment, and not to create electrical disturbances that would interfere with other equipment.

The electromagnetic susceptibility (EMS) level of a device is the resistance to electrical disturbances and conducted electrical noise. Electrostatic discharge (ESD) and fast transient burst (FTB) tests determine the reliability level of a device operating in an undesirable electromagnetic environment.

The electromagnetic interference (EMI) is the level of conducted or radiated electrical noise sourced by the equipment. Conducted emission propagates along a cable or any interconnection line. Radiated emission propagates through free space.

Functional tests are performed to measure the robustness of microcontrollers running in an application. Based on a simple program (toggling two LEDs through I/O ports), the product is stressed by two different EMC events until a run-away condition (failure) occurs.

This test is performed on any new microcontroller devices. Each pin is tested individually with a single positive or negative electrical discharge. This allows failures investigations inside the chip and further application recommendations to protect the concerned microcontroller sensitive pins against ESD.

The equipment used to perform F_ESD test is an NSG 435 generator (TESEQ) compliant with the IEC 61000-4-2 standard. The discharges are directly applied on each pin of the MCU.

Measurements are performed on a ground plane. The generator is connected to ground plane by a short wire. The supply wires are 10 cm from the ground plane. The DUT is on the insulator 10 cm from the ground plane. The FTB voltage level is increased until the device failure.

Severity levels and class help application designers to determine which microcontrollers are suitable for their target application, based on the susceptibility level (severity level) and type of behavior (class) indicated in the datasheet.

This test is performed to assess the components immunity against destruction caused by ESD. Any device that fails this electrical test program is classified as a failure.

Using automatic ESD tester, electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3parts*(n+1), where n = supply pins).

Two models are usually simulated: human body model (HBM) and the charge device model (CDM). All parts are re-tested on the production tester to verify the static and dynamic parameters still comply with the device datasheet (see Figure 6 Absolute electrical sensitivity test models).

For both models, parts are not powered during the ESD stress. This test conforms to the JESD22-A114A/A115A standard. See Figure 6 Absolute electrical sensitivity test models and the following test sequences.

This test correlates with the IEC 61967-2 standard. It gives a good evaluation of the contribution of the microcontroller to radiated noise in an application environment. It takes into account the MCU chip as well as the package, which has a major influence on the noise radiated by the device.

In general, the smaller the package belonging to a given package family, the lower the noise generated.

The EMI classifications are based on IEC61967-2 international standard–Annex D-3 (see Figure 9 IEC61967-2 classification chart).

The characterization level diagram described by this standard provides a synthesis and a classification of the EMI spectrum. It uses the patterns defined by a combination of one or two letters for horizontal lines and one number for diagonal line. From these patterns, four typical patterns have been selected for ST internal classification (see Figure 10 ST internal EMI level classification) to estimate the EMI risk for each microcontroller. This selection considers the resolution bandwidth of used spectrum analyzer as well as resonances caused by the geometry of the test board and setup of the test bench.

When the overstepping of a particular limit is not significant, and the corresponding peak values of the interference lie approximately in the middle between two patterns, then half-levels might be used as well.

During the initial specification phase of a new product, EMC dedicated features are implemented after an identification of EMC constraints. It is the MCU target applications that impose these constraints. Refer to the specific product datasheet to know which of these features described in the figure below are embedded.

The purpose of the BOR is to ensure that the microcontroller always work in its safe operating area (see Figure 13 Using the PVD to monitor V DD). In terms of EMS, the presence of the BOR makes the MCU more robust. It also ensures that if any outside disturbance affects the power supply, the application can recover safely.

When V_DD is below the minimum working V_DD, the behavior of the microcontroller is no longer guaranteed. There is not enough power to decode/execute the instructions and/or read the memory. When V_DD is below the BOR level, the microcontroller enters in reset state (internal reset high) in order to prevent unpredictable behavior.

There are several levels with hysteresis in order to avoid oscillating when the micro restarts. When a BOR occurs, the hardware set a bit. This bit is used to recover an application.

The brownout reset function generates a static reset when the V_DD supply voltage is below a V_IT- reference value. This means that it secures the power-up as well as the power-down, keeping the microcontroller in reset (see Figure 12 Brownout reset versus reset).

The V_IT- reference value for a voltage drop is lower than the V_IT+ reference value for power-on to avoid a parasitic reset. This is the case when the MCU starts running and sinks current on the supply (hysteresis).

This feature like the BOR improves EMS performance. It ensures that the microcontroller behaves safely when the power supply is disturbed by external noise.

The PVD has also different levels (around 200 mV above BOR levels), it enables an early warning before the reset caused by the BOR. When PVD threshold is crossed, an interrupt is generated, requesting for example some user action or preparing the application to shut down in the interrupt routine until the power supply returns to the correct level for the device (refer to the product datasheet).

Integrated circuit datasheets provide the user with conservative limits and conditions to prevent damage. However, it is useful for the hardware system designer to know the internal failure mechanisms. Ultimately the risk of exposure to illegal voltages and conditions can be reduced.

It is not possible to classify and to predict all the possible damage resulting from violating maximum ratings and conditions. This is due to the large number of variables that come into play in defining the failures. This means that when an overvoltage condition is applied, the effects on the device can vary significantly. Consequently, it depends on lot-to-lot process variations, operating temperature, external interfacing of the microcontroller with other devices.

In the following sections, background technical information is given to help system designers to reduce the risk of damage to the microcontroller device.

Some microcontrollers have an embedded programmable PLL clock generator that allows the usage of standard 3 MHz to 25 MHz crystals. This allows a large range of internal frequencies (up to a few hundred MHz) to be obtained. By these means, the microcontroller can operate with cheaper, medium frequency crystals, while still providing a high frequency internal clock for maximum system performance. The high-clock frequency source is contained inside the chip and does not go through the PCB (printed circuit board) tracks and external components. This reduces the potential noise emission of the application.

The use of the PLL network also filters the CPU clock against external sporadic disturbances (glitches).

Output buffers are embedded in microcontrollers. Their switching speed is controlled in order to avoid parasitic oscillations when they are switched. The MCU design makes a trade-off between noise and speed.

The following guidelines result from the experience gained in a wide variety of applications.

The major noise receptors and generators are the tracks and wiring on the printed circuit board (PCB), especially those near the MCU. The first actions to prevent noise problems thus concern the PCB layout and the design of the power supply.

In general, the smaller the number of components surrounding the MCU, the better the immunity versus noise. A ROMless solution, for instance, is typically more sensitive to and a bigger generator of noise than an embedded memory circuit.

Noise is basically received and transmitted through tracks and components which, once excited, act as antennas. Each loop and track includes parasitic inductance and capacitance. This radiate and absorb energy once submitted to a variation of current, voltage, or electromagnetic flux.

An MCU chip itself presents high immunity to and low generation of EMI since its dimensions are small versus the wave lengths of EMI signals (typically mm versus 10's of cm for EMI signals in the GHz range). Therefore, a single chip solution with small loops and short wires reduces noise problems.

The initial action at the PCB level is to reduce the number of possible antennas. The loops and wires connected to the MCU such as supply, oscillator and I/O must be considered with a special attention. The oscillator loop must be especially small since it operates at high frequency (see Figure 17 PCB board-oscillator layout examples).

A reduction of both the inductance and the capacitance of a track is generally difficult. The practical experience suggests that in most cases inductance is the first parameter to minimize.

The reduction of inductance is obtained by making the lengths and surfaces of the track smaller. This is performed placing the track loops closer on the same PCB layer or on top of one another (Figure 17 PCB board-oscillator layout examples). The resulting loop area is small and the electromagnetic fields reduce one another.

The ratio in order of magnitude relating to the inductance value and the area defined by the wire loop is around 10 nH/cm2. Typical examples of low inductivity wires are coaxial, twisted pair cables or multiple layer PCBs with one ground and one supply layers. The current density in the track can also be smaller due to track enlargement or the paralleling of several small capacitances mounted in the current flow.

The power supply is used by all parts of the circuit, therefore it must be considered with special attention. The supply loops must be decoupled to make sure that signal levels and power currents do not interfere. These loops can be separated using star wiring with one node designated as common for the circuit (Figure 19 Power-supply layout examples).

The decoupling capacitance must be placed very close to the MCU supply pins to minimize the resultant loop. It should be also large enough to absorb, without significant voltage increase, parasitic currents coming from the MCU via the input protection diodes. The decoupling of the board can be done with electrolytic capacitors (typically 10 µF to 100 µF) since the dielectric used in such capacitors provides a high volumic capacitance. However, these capacitors behave like inductances at high frequency (typically above10 MHz) while ceramic or plastic capacitors keep a capacitive behavior at higher frequency.

A ceramic capacitance of, for instance, 0.1 μF to 1 μF must be used as high-frequency supply decoupling for critical chips operating at high frequency.

It is recommended to connect all VSS pins together by the shortest possible path to reduce the risk of creating voltage difference between the VSS pins above the absolute maximum ratings stated in the device datasheet, due to the current induced by external disturbance and to reduce the impedance of ground return path.

The best practice is to connect the VSS lines to the ground plane through the vias placed as close as possible to the device VSS pins. The ground plane must be solid without slots or holes, which may cause an increase of the ground plane impedance. The split of analog and digital ground is not recommended. While it may have a questionable impact on noise distribution from the digital-to-analog domain, it shows always worse EMC performance.

A digital input configuration with the pin floating is a potential hazard to the circuit. It is recommended that I/O pins not used in the application be configured in output push-pull low state. This increases EMC robustness or configure as an analog input connected to ground to reduce power current consumption.

Shielding helps to reduce noise sensitivity and emission. However, it depends on the material chosen as a shield. It must have a high permeability or a low resistivity, and its connection must be to a stable voltage source. This includes a decoupling capacitance via a low serial impedance (low inductance or low resistance) voltage source.

If the generator of major disturbances is near to the MCU board and identified as a strong dV/dt generator (that is, a transformer or klystron), the noise is carried mainly by the electrostatic field. The critical coupling between the noise generator and the control board is capacitive. A highly conductive shield that is, copper, creating a faraday cage around the control board may strongly increase the immunity.

If the strongest source of perturbations is a dI/dt generator (that is, a relay), it is a high source of electromagnetic fields. Therefore, the permeability of the shielding material namely alloy, is crucial to increase the immunity of the board. In addition, the number and size of the holes on the shield should be reduced as much as possible to increase its efficiency.

In critical cases, the implantation of a ground plane below the MCU, and the removal of sockets between the device and the PCB can reduce the MCU noise sensitivity. Indeed, both actions lead to a reduction of the apparent surface of loops between the MCU, its supply, its I/O and the PCB.

In some application cases, when the ESD strike occurs on a pin PA3 then, the adjacent pins PA2 and PA4 can be affected by a voltage spike transferred to the current.