DAC 2022

10-14 July – Moscone West Center – San Francisco, CA, USA

More info on DAC: www.dac.com
Register here
Full agenda


59th Design Automation Conference

Founded in 1964, DAC is the longest-running and largest event focused on research and technology for the design and the design automation of electronic chips to systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.

This year ST will demonstrate its innovative solutions and methodologies in the field of not only designs but also how to build them. ST's experts will share their visions in the new era of design and verification flows, helping engineers design and create state-of-the-art solutions and reach the market on time while ensuring the highest quality. Follow us at DAC.  We have several paper and poster presentations on the agenda showcasing our latest research on a variety of focus areas. You will also find us in the Gladiator Arena!

PAPER Presentation    
Novel Approach to Early detection of Metastability related issues Monday July 11
10:30-10:45 am PDT
Session: Taming the Validation Dragon with Formal and Static Verification
Alessandro Giuliano Locardi
ST presenter
Andrea Lopinto, ST co-author
Verifying Register Maps with JasperGold: How Formal compares to UVM Monday July 11
10:45-11 am PDT
Session: Taming the Validation Dragon with Formal and Static Verification
Davide Sanalitro
ST presenter
Edoardo Bollea
ST co-author
Memory Read Yield Estimation Using High Sigma Monte Carlo Monday July 11
3:30-3:45 pm PTD
When RTL doesn't cut it: topics in analog, mixed signal and custom IP design
Ashish Kumar
ST presenter
Verifying I/O Designs Using Formal Techniques to Increase Design and Model Robustness Monday July 11
4-4:15 pm PDT
Session: When RTL doesn't cut it: topics in analog, mixed signal and custom IP design
Moninder Singh
Synopsis presenter
Natish Singla
ST main author
Characterization Challenges in System Level IO Interface Wedesday July 13
1:30-1:45 pm PDT
Session: Lifecycle of design elements
Tina Durgia, Wei Lii Tan
Mentor presenters
Saurabh Srivastava
ST author

 

POSTER PRESENTATIONS    
Using Formal Verification Signoff for Digital IP POSTER Gladiator
Monday 11 July
5-6 pm PDT
Engineering Track poster reception
David Vincenzoni
ST presenter
Ensuring Accurate Crosstalk Analysis using CCS-Noise Liberty Model Tuesday 12 July
5-6 pm PDT
Engineering Track poster reception
Atul Bhargava
ST Presenter
Rahul Kumar
ST main author
Integrating Liberty model validation, analysis, and visualization as part of library design and characterization Tuesday July 12
5-6 pm PTD
Engineering Track poster reception
Austin Shirley – Tina Durgia
Mentor presenters
Saurabh Srivastava
ST main author
A unified IP QA methodology to improve validation coverage and throughput POSTER Gladiator
Tuesday 12 July
5-6 pm PTD
Wei Lii Tan
Siemens Presenter
Lippika Parwani
ST main author
SDR (Simulation-Driven Routing) - A Solution to Get Electromigration Compliant Routing Tuesday July 12
5-6 pm PDT
Engineering track poster reception
Bryan Laborde
Cadence Presenter
Lippika Parwani
ST main author
On-Chip embedded sensor in 18nm technology to monitor the effects of process variations on standard cells logic and interconnect delays Wednesday July 13
5-6 pm PDT
Engineering Track poster reception
Rohit Kumar Gupta
ST presenter
Rohit Goel
ST Author
Process Monitoring Blocks (PMB) - for Monitoring Analog Performance Wednesday July 13
5-6 pm PDT
Engineering Track poster reception
Rohit Kumar Gupta
ST presenter
Priya Ashu Talwar
ST Author
Design-Technology co-optimization to mitigate the technology impact of context-based timing in standard Cell POSTER Gladiator
Wednesday July 13
5-6 pm PDT
Engineering Track poster reception
Rohit Kumar Gupta
ST Presenter
Veny Mahajan
ST main author
Design Intent Driven Analog Routing Methodology Wednesday July 13
5-6 pm PTD
Engineering Track poster reception
Atul Bhargava
ST Presenter
Rajeev Singh
ST main author
Streamlined solution for CAD views generation & validation of AMS IP for SOC enablement Wednesday July 13
5-6 pm PDT
Engineering Track poster reception
Atul Bhargava
ST presenter
Lippika Parwani
ST Main author